Intel has a processor with up to 48 cores presented. The cores are grouped in 24 pairs each of which has its own L2 cache available. The cpu’s are in a very small series released and are intended only for research.
The 48 cores are divided into 24-dualcore’tegels’, beside the two cores, each with their own L2 cache from a message buffer and a router there. The message buffer ensures communication between the cores on a tile and the router handles the exchange between different tiles, making a mesh network with a bandwidth of 256GB / s arises. Six tiles share a memory controller, which cooperate with four DDR3 memory up to 32GB to speak. Each core has 384KB cache memory and the software can be shared between cores, thus slowing the effects of synchronous caches between cores disappear.